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<div class="header">
  <div class="headertitle"><div class="title">TIM Output Compare and PWM Modes <div class="ingroups"><a class="el" href="group___s_t_m32_h7xx___h_a_l___driver.html">STM32H7xx_HAL_Driver</a> &raquo; <a class="el" href="group___t_i_m.html">TIM</a> &raquo; <a class="el" href="group___t_i_m___exported___constants.html">TIM Exported Constants</a></div></div></div>
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<table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 id="header-define-members" class="groupheader"><a id="define-members" name="define-members"></a>
Macros</h2></td></tr>
<tr class="memitem:gafae6b98b4b854fbfffd9a5ebc59c8f61" id="r_gafae6b98b4b854fbfffd9a5ebc59c8f61"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#gafae6b98b4b854fbfffd9a5ebc59c8f61">TIM_OCMODE_TIMING</a>&#160;&#160;&#160;0x00000000U</td></tr>
<tr class="memitem:ga111d1023e3ac6ef5544775c3863b4b12" id="r_ga111d1023e3ac6ef5544775c3863b4b12"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ga111d1023e3ac6ef5544775c3863b4b12">TIM_OCMODE_ACTIVE</a>&#160;&#160;&#160;<a class="el" href="group___peripheral___registers___bits___definition.html#ga410a4752a98081bad8ab3f72b28e7c5f">TIM_CCMR1_OC1M_0</a></td></tr>
<tr class="memitem:ga890fbb44fd16f2bce962983352d23f53" id="r_ga890fbb44fd16f2bce962983352d23f53"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ga890fbb44fd16f2bce962983352d23f53">TIM_OCMODE_INACTIVE</a>&#160;&#160;&#160;<a class="el" href="group___peripheral___registers___bits___definition.html#ga8b5f6ec25063483641d6dc065d96d2b5">TIM_CCMR1_OC1M_1</a></td></tr>
<tr class="memitem:ga368f80fad76018e2bf76084522e47536" id="r_ga368f80fad76018e2bf76084522e47536"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ga368f80fad76018e2bf76084522e47536">TIM_OCMODE_TOGGLE</a>&#160;&#160;&#160;(<a class="el" href="group___peripheral___registers___bits___definition.html#ga8b5f6ec25063483641d6dc065d96d2b5">TIM_CCMR1_OC1M_1</a> | <a class="el" href="group___peripheral___registers___bits___definition.html#ga410a4752a98081bad8ab3f72b28e7c5f">TIM_CCMR1_OC1M_0</a>)</td></tr>
<tr class="memitem:ga766271da571888dfecd9130c3887e9c6" id="r_ga766271da571888dfecd9130c3887e9c6"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ga766271da571888dfecd9130c3887e9c6">TIM_OCMODE_PWM1</a>&#160;&#160;&#160;(<a class="el" href="group___peripheral___registers___bits___definition.html#gac024f6b9972b940925ab5786ee38701b">TIM_CCMR1_OC1M_2</a> | <a class="el" href="group___peripheral___registers___bits___definition.html#ga8b5f6ec25063483641d6dc065d96d2b5">TIM_CCMR1_OC1M_1</a>)</td></tr>
<tr class="memitem:ga88ce4251743c2c07e19fdd5a0a310580" id="r_ga88ce4251743c2c07e19fdd5a0a310580"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ga88ce4251743c2c07e19fdd5a0a310580">TIM_OCMODE_PWM2</a>&#160;&#160;&#160;(<a class="el" href="group___peripheral___registers___bits___definition.html#gac024f6b9972b940925ab5786ee38701b">TIM_CCMR1_OC1M_2</a> | <a class="el" href="group___peripheral___registers___bits___definition.html#ga8b5f6ec25063483641d6dc065d96d2b5">TIM_CCMR1_OC1M_1</a> | <a class="el" href="group___peripheral___registers___bits___definition.html#ga410a4752a98081bad8ab3f72b28e7c5f">TIM_CCMR1_OC1M_0</a>)</td></tr>
<tr class="memitem:ga0a78cecaf884a89963e2a8e6af7e6128" id="r_ga0a78cecaf884a89963e2a8e6af7e6128"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ga0a78cecaf884a89963e2a8e6af7e6128">TIM_OCMODE_FORCED_ACTIVE</a>&#160;&#160;&#160;(<a class="el" href="group___peripheral___registers___bits___definition.html#gac024f6b9972b940925ab5786ee38701b">TIM_CCMR1_OC1M_2</a> | <a class="el" href="group___peripheral___registers___bits___definition.html#ga410a4752a98081bad8ab3f72b28e7c5f">TIM_CCMR1_OC1M_0</a>)</td></tr>
<tr class="memitem:ga4572f724ce30ce45557f1dc5141afb3e" id="r_ga4572f724ce30ce45557f1dc5141afb3e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ga4572f724ce30ce45557f1dc5141afb3e">TIM_OCMODE_FORCED_INACTIVE</a>&#160;&#160;&#160;<a class="el" href="group___peripheral___registers___bits___definition.html#gac024f6b9972b940925ab5786ee38701b">TIM_CCMR1_OC1M_2</a></td></tr>
<tr class="memitem:ga53168a4498dcb4956d9f84419a20841c" id="r_ga53168a4498dcb4956d9f84419a20841c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ga53168a4498dcb4956d9f84419a20841c">TIM_OCMODE_RETRIGERRABLE_OPM1</a>&#160;&#160;&#160;<a class="el" href="group___peripheral___registers___bits___definition.html#gac93dfe7865726bc84363684b9fa01c93">TIM_CCMR1_OC1M_3</a></td></tr>
<tr class="memitem:ga83f39ecc55403f37e930e6f14cb6cc76" id="r_ga83f39ecc55403f37e930e6f14cb6cc76"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ga83f39ecc55403f37e930e6f14cb6cc76">TIM_OCMODE_RETRIGERRABLE_OPM2</a>&#160;&#160;&#160;(<a class="el" href="group___peripheral___registers___bits___definition.html#gac93dfe7865726bc84363684b9fa01c93">TIM_CCMR1_OC1M_3</a> | <a class="el" href="group___peripheral___registers___bits___definition.html#ga410a4752a98081bad8ab3f72b28e7c5f">TIM_CCMR1_OC1M_0</a>)</td></tr>
<tr class="memitem:gaa13e0cb2370d61cfee1241498733b38b" id="r_gaa13e0cb2370d61cfee1241498733b38b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#gaa13e0cb2370d61cfee1241498733b38b">TIM_OCMODE_COMBINED_PWM1</a>&#160;&#160;&#160;(<a class="el" href="group___peripheral___registers___bits___definition.html#gac93dfe7865726bc84363684b9fa01c93">TIM_CCMR1_OC1M_3</a> | <a class="el" href="group___peripheral___registers___bits___definition.html#gac024f6b9972b940925ab5786ee38701b">TIM_CCMR1_OC1M_2</a>)</td></tr>
<tr class="memitem:gaf983419ff3d5bc0ca8d122bb8f321eff" id="r_gaf983419ff3d5bc0ca8d122bb8f321eff"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#gaf983419ff3d5bc0ca8d122bb8f321eff">TIM_OCMODE_COMBINED_PWM2</a>&#160;&#160;&#160;(<a class="el" href="group___peripheral___registers___bits___definition.html#gac93dfe7865726bc84363684b9fa01c93">TIM_CCMR1_OC1M_3</a> | <a class="el" href="group___peripheral___registers___bits___definition.html#ga410a4752a98081bad8ab3f72b28e7c5f">TIM_CCMR1_OC1M_0</a> | <a class="el" href="group___peripheral___registers___bits___definition.html#gac024f6b9972b940925ab5786ee38701b">TIM_CCMR1_OC1M_2</a>)</td></tr>
<tr class="memitem:gac1c1f898f74a95c15bd1cee91c636a82" id="r_gac1c1f898f74a95c15bd1cee91c636a82"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#gac1c1f898f74a95c15bd1cee91c636a82">TIM_OCMODE_ASYMMETRIC_PWM1</a>&#160;&#160;&#160;(<a class="el" href="group___peripheral___registers___bits___definition.html#gac93dfe7865726bc84363684b9fa01c93">TIM_CCMR1_OC1M_3</a> | <a class="el" href="group___peripheral___registers___bits___definition.html#ga8b5f6ec25063483641d6dc065d96d2b5">TIM_CCMR1_OC1M_1</a> | <a class="el" href="group___peripheral___registers___bits___definition.html#gac024f6b9972b940925ab5786ee38701b">TIM_CCMR1_OC1M_2</a>)</td></tr>
<tr class="memitem:ga475c44a172e981d0d96e51dd811d2705" id="r_ga475c44a172e981d0d96e51dd811d2705"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ga475c44a172e981d0d96e51dd811d2705">TIM_OCMODE_ASYMMETRIC_PWM2</a>&#160;&#160;&#160;<a class="el" href="group___peripheral___registers___bits___definition.html#ga6ddb3dc889733e71d812baa3873cb13b">TIM_CCMR1_OC1M</a></td></tr>
</table>
<a name="details" id="details"></a><h2 id="header-details" class="groupheader">Detailed Description</h2>
<a name="doc-define-members" id="doc-define-members"></a><h2 id="header-doc-define-members" class="groupheader">Macro Definition Documentation</h2>
<a id="ga111d1023e3ac6ef5544775c3863b4b12" name="ga111d1023e3ac6ef5544775c3863b4b12"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga111d1023e3ac6ef5544775c3863b4b12">&#9670;&#160;</a></span>TIM_OCMODE_ACTIVE</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define TIM_OCMODE_ACTIVE&#160;&#160;&#160;<a class="el" href="group___peripheral___registers___bits___definition.html#ga410a4752a98081bad8ab3f72b28e7c5f">TIM_CCMR1_OC1M_0</a></td>
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      </table>
</div><div class="memdoc">
<p>Set channel to active level on match </p>

</div>
</div>
<a id="gac1c1f898f74a95c15bd1cee91c636a82" name="gac1c1f898f74a95c15bd1cee91c636a82"></a>
<h2 class="memtitle"><span class="permalink"><a href="#gac1c1f898f74a95c15bd1cee91c636a82">&#9670;&#160;</a></span>TIM_OCMODE_ASYMMETRIC_PWM1</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define TIM_OCMODE_ASYMMETRIC_PWM1&#160;&#160;&#160;(<a class="el" href="group___peripheral___registers___bits___definition.html#gac93dfe7865726bc84363684b9fa01c93">TIM_CCMR1_OC1M_3</a> | <a class="el" href="group___peripheral___registers___bits___definition.html#ga8b5f6ec25063483641d6dc065d96d2b5">TIM_CCMR1_OC1M_1</a> | <a class="el" href="group___peripheral___registers___bits___definition.html#gac024f6b9972b940925ab5786ee38701b">TIM_CCMR1_OC1M_2</a>)</td>
        </tr>
      </table>
</div><div class="memdoc">
<p>Asymmetric PWM mode 1 </p>

</div>
</div>
<a id="ga475c44a172e981d0d96e51dd811d2705" name="ga475c44a172e981d0d96e51dd811d2705"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga475c44a172e981d0d96e51dd811d2705">&#9670;&#160;</a></span>TIM_OCMODE_ASYMMETRIC_PWM2</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define TIM_OCMODE_ASYMMETRIC_PWM2&#160;&#160;&#160;<a class="el" href="group___peripheral___registers___bits___definition.html#ga6ddb3dc889733e71d812baa3873cb13b">TIM_CCMR1_OC1M</a></td>
        </tr>
      </table>
</div><div class="memdoc">
<p>Asymmetric PWM mode 2 </p>

</div>
</div>
<a id="gaa13e0cb2370d61cfee1241498733b38b" name="gaa13e0cb2370d61cfee1241498733b38b"></a>
<h2 class="memtitle"><span class="permalink"><a href="#gaa13e0cb2370d61cfee1241498733b38b">&#9670;&#160;</a></span>TIM_OCMODE_COMBINED_PWM1</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define TIM_OCMODE_COMBINED_PWM1&#160;&#160;&#160;(<a class="el" href="group___peripheral___registers___bits___definition.html#gac93dfe7865726bc84363684b9fa01c93">TIM_CCMR1_OC1M_3</a> | <a class="el" href="group___peripheral___registers___bits___definition.html#gac024f6b9972b940925ab5786ee38701b">TIM_CCMR1_OC1M_2</a>)</td>
        </tr>
      </table>
</div><div class="memdoc">
<p>Combined PWM mode 1 </p>

</div>
</div>
<a id="gaf983419ff3d5bc0ca8d122bb8f321eff" name="gaf983419ff3d5bc0ca8d122bb8f321eff"></a>
<h2 class="memtitle"><span class="permalink"><a href="#gaf983419ff3d5bc0ca8d122bb8f321eff">&#9670;&#160;</a></span>TIM_OCMODE_COMBINED_PWM2</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define TIM_OCMODE_COMBINED_PWM2&#160;&#160;&#160;(<a class="el" href="group___peripheral___registers___bits___definition.html#gac93dfe7865726bc84363684b9fa01c93">TIM_CCMR1_OC1M_3</a> | <a class="el" href="group___peripheral___registers___bits___definition.html#ga410a4752a98081bad8ab3f72b28e7c5f">TIM_CCMR1_OC1M_0</a> | <a class="el" href="group___peripheral___registers___bits___definition.html#gac024f6b9972b940925ab5786ee38701b">TIM_CCMR1_OC1M_2</a>)</td>
        </tr>
      </table>
</div><div class="memdoc">
<p>Combined PWM mode 2 </p>

</div>
</div>
<a id="ga0a78cecaf884a89963e2a8e6af7e6128" name="ga0a78cecaf884a89963e2a8e6af7e6128"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga0a78cecaf884a89963e2a8e6af7e6128">&#9670;&#160;</a></span>TIM_OCMODE_FORCED_ACTIVE</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define TIM_OCMODE_FORCED_ACTIVE&#160;&#160;&#160;(<a class="el" href="group___peripheral___registers___bits___definition.html#gac024f6b9972b940925ab5786ee38701b">TIM_CCMR1_OC1M_2</a> | <a class="el" href="group___peripheral___registers___bits___definition.html#ga410a4752a98081bad8ab3f72b28e7c5f">TIM_CCMR1_OC1M_0</a>)</td>
        </tr>
      </table>
</div><div class="memdoc">
<p>Force active level </p>

</div>
</div>
<a id="ga4572f724ce30ce45557f1dc5141afb3e" name="ga4572f724ce30ce45557f1dc5141afb3e"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga4572f724ce30ce45557f1dc5141afb3e">&#9670;&#160;</a></span>TIM_OCMODE_FORCED_INACTIVE</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define TIM_OCMODE_FORCED_INACTIVE&#160;&#160;&#160;<a class="el" href="group___peripheral___registers___bits___definition.html#gac024f6b9972b940925ab5786ee38701b">TIM_CCMR1_OC1M_2</a></td>
        </tr>
      </table>
</div><div class="memdoc">
<p>Force inactive level </p>

</div>
</div>
<a id="ga890fbb44fd16f2bce962983352d23f53" name="ga890fbb44fd16f2bce962983352d23f53"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga890fbb44fd16f2bce962983352d23f53">&#9670;&#160;</a></span>TIM_OCMODE_INACTIVE</h2>

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          <td class="memname">#define TIM_OCMODE_INACTIVE&#160;&#160;&#160;<a class="el" href="group___peripheral___registers___bits___definition.html#ga8b5f6ec25063483641d6dc065d96d2b5">TIM_CCMR1_OC1M_1</a></td>
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</div><div class="memdoc">
<p>Set channel to inactive level on match </p>

</div>
</div>
<a id="ga766271da571888dfecd9130c3887e9c6" name="ga766271da571888dfecd9130c3887e9c6"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga766271da571888dfecd9130c3887e9c6">&#9670;&#160;</a></span>TIM_OCMODE_PWM1</h2>

<div class="memitem">
<div class="memproto">
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          <td class="memname">#define TIM_OCMODE_PWM1&#160;&#160;&#160;(<a class="el" href="group___peripheral___registers___bits___definition.html#gac024f6b9972b940925ab5786ee38701b">TIM_CCMR1_OC1M_2</a> | <a class="el" href="group___peripheral___registers___bits___definition.html#ga8b5f6ec25063483641d6dc065d96d2b5">TIM_CCMR1_OC1M_1</a>)</td>
        </tr>
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</div><div class="memdoc">
<p>PWM mode 1 </p>

</div>
</div>
<a id="ga88ce4251743c2c07e19fdd5a0a310580" name="ga88ce4251743c2c07e19fdd5a0a310580"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga88ce4251743c2c07e19fdd5a0a310580">&#9670;&#160;</a></span>TIM_OCMODE_PWM2</h2>

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          <td class="memname">#define TIM_OCMODE_PWM2&#160;&#160;&#160;(<a class="el" href="group___peripheral___registers___bits___definition.html#gac024f6b9972b940925ab5786ee38701b">TIM_CCMR1_OC1M_2</a> | <a class="el" href="group___peripheral___registers___bits___definition.html#ga8b5f6ec25063483641d6dc065d96d2b5">TIM_CCMR1_OC1M_1</a> | <a class="el" href="group___peripheral___registers___bits___definition.html#ga410a4752a98081bad8ab3f72b28e7c5f">TIM_CCMR1_OC1M_0</a>)</td>
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<p>PWM mode 2 </p>

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<h2 class="memtitle"><span class="permalink"><a href="#ga53168a4498dcb4956d9f84419a20841c">&#9670;&#160;</a></span>TIM_OCMODE_RETRIGERRABLE_OPM1</h2>

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          <td class="memname">#define TIM_OCMODE_RETRIGERRABLE_OPM1&#160;&#160;&#160;<a class="el" href="group___peripheral___registers___bits___definition.html#gac93dfe7865726bc84363684b9fa01c93">TIM_CCMR1_OC1M_3</a></td>
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<p>Retrigerrable OPM mode 1 </p>

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<h2 class="memtitle"><span class="permalink"><a href="#ga83f39ecc55403f37e930e6f14cb6cc76">&#9670;&#160;</a></span>TIM_OCMODE_RETRIGERRABLE_OPM2</h2>

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          <td class="memname">#define TIM_OCMODE_RETRIGERRABLE_OPM2&#160;&#160;&#160;(<a class="el" href="group___peripheral___registers___bits___definition.html#gac93dfe7865726bc84363684b9fa01c93">TIM_CCMR1_OC1M_3</a> | <a class="el" href="group___peripheral___registers___bits___definition.html#ga410a4752a98081bad8ab3f72b28e7c5f">TIM_CCMR1_OC1M_0</a>)</td>
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<p>Retrigerrable OPM mode 2 </p>

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<h2 class="memtitle"><span class="permalink"><a href="#gafae6b98b4b854fbfffd9a5ebc59c8f61">&#9670;&#160;</a></span>TIM_OCMODE_TIMING</h2>

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          <td class="memname">#define TIM_OCMODE_TIMING&#160;&#160;&#160;0x00000000U</td>
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<p>Frozen </p>

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<a id="ga368f80fad76018e2bf76084522e47536" name="ga368f80fad76018e2bf76084522e47536"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga368f80fad76018e2bf76084522e47536">&#9670;&#160;</a></span>TIM_OCMODE_TOGGLE</h2>

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          <td class="memname">#define TIM_OCMODE_TOGGLE&#160;&#160;&#160;(<a class="el" href="group___peripheral___registers___bits___definition.html#ga8b5f6ec25063483641d6dc065d96d2b5">TIM_CCMR1_OC1M_1</a> | <a class="el" href="group___peripheral___registers___bits___definition.html#ga410a4752a98081bad8ab3f72b28e7c5f">TIM_CCMR1_OC1M_0</a>)</td>
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<p>Toggle </p>

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